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HPCA
2004
IEEE
16 years 3 months ago
Out-of-Order Commit Processors
Modern out-of-order processors tolerate long latency memory operations by supporting a large number of inflight instructions. This is particularly useful in numerical applications...
Adrián Cristal, Daniel Ortega, Josep Llosa,...
101
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ISCA
2007
IEEE
90views Hardware» more  ISCA 2007»
15 years 9 months ago
Transparent control independence (TCI)
AL-ZAWAWI, AHMED SAMI. Transparent Control Independence (TCI). (Under the direction of Dr. Eric Rotenberg). Superscalar architectures have been proposed that exploit control indep...
Ahmed S. Al-Zawawi, Vimal K. Reddy, Eric Rotenberg...
ENTCS
2002
166views more  ENTCS 2002»
15 years 3 months ago
Translation and Run-Time Validation of Optimized Code
The paper presents approaches to the validation of optimizing compilers. The emphasis is on aggressive and architecture-targeted optimizations which try to obtain the highest perf...
Lenore D. Zuck, Amir Pnueli, Yi Fang, Benjamin Gol...
SASP
2009
IEEE
291views Hardware» more  SASP 2009»
15 years 10 months ago
A parameterisable and scalable Smith-Waterman algorithm implementation on CUDA-compatible GPUs
—This paper describes a multi-threaded parallel design and implementation of the Smith-Waterman (SM) algorithm on compute unified device architecture (CUDA)-compatible graphic pr...
Cheng Ling, Khaled Benkrid, Tsuyoshi Hamada
IEEEPACT
2005
IEEE
15 years 9 months ago
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
Huiyang Zhou