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TVLSI
2002
100views more  TVLSI 2002»
13 years 9 months ago
Architectural strategies for low-power VLSI turbo decoders
Abstract--The use of "turbo codes" has been proposed for several applications, including the development of wireless systems, where highly reliable transmission is requir...
Guido Masera, M. Mazza, Gianluca Piccinini, F. Vig...
ICPP
2009
IEEE
13 years 8 months ago
A Resource Optimized Remote-Memory-Access Architecture for Low-latency Communication
This paper introduces a new highly optimized architecture for remote memory access (RMA). RMA, using put and get operations, is a one-sided communication function which amongst ot...
Mondrian Nüssle, Martin Scherer, Ulrich Br&uu...
MICRO
2007
IEEE
184views Hardware» more  MICRO 2007»
14 years 4 months ago
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures
The recent design shift towards multicore processors has spawned a significant amount of research in the area of program parallelization. The future abundance of cores on a singl...
Michael L. Chu, Rajiv A. Ravindran, Scott A. Mahlk...
SIGCOMM
2000
ACM
14 years 2 months ago
SmartBridge: A scalable bridge architecture
As the number of hosts attached to a network increases beyond what can be connected by a single local area network (LAN), forwarding packets between hosts on different LANs become...
Thomas L. Rodeheffer, Chandramohan A. Thekkath, Da...
CIIA
2009
13 years 11 months ago
Physical Synthesis for CPLD Architectures
In this paper, we present a new synthesis feature namely, "Xor matching", and the foldback product term synthesis for Complex Programmable Logic Devices (CPLD) architectu...
Sid-Ahmed Senouci