Sciweavers

1602 search results - page 166 / 321
» Database Architectures for New Hardware
Sort
View
ISPAN
2005
IEEE
14 years 2 months ago
Process Scheduling for the Parallel Desktop
Commodity hardware and software are growing increasingly more complex, with advances such as chip heterogeneity and specialization, deeper memory hierarchies, ne-grained power ma...
Eitan Frachtenberg
EGH
2004
Springer
14 years 2 months ago
A quadrilateral rendering primitive
The only surface primitives that are supported by common graphics hardware are triangles and more complex shapes have to be triangulated before being sent to the rasterizer. Even ...
Kai Hormann, Marco Tarini
ICCD
2008
IEEE
159views Hardware» more  ICCD 2008»
14 years 6 months ago
Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor
— Heterogeneous Chip Multiprocessors (HMPs), such as the Cell Broadband Engine, offer a new design optimization opportunity by allowing designers to provide accelerators for appl...
Michael Gschwind
MICRO
1993
IEEE
93views Hardware» more  MICRO 1993»
14 years 1 months ago
Speculative execution exception recovery using write-back suppression
Compiler-controlled speculative execution has been shown to be e ective in increasing the availableinstruction level parallelismILP found in non-numeric programs. An importantpr...
Roger A. Bringmann, Scott A. Mahlke, Richard E. Ha...
CODES
2005
IEEE
14 years 2 months ago
FlexPath NP: a network processor concept with application-driven flexible processing paths
In this paper, we present a new architectural concept for network processors called FlexPath NP. The central idea behind FlexPath NP is to systematically map network processor (NP...
Rainer Ohlendorf, Andreas Herkersdorf, Thomas Wild