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DATE
2010
IEEE
163views Hardware» more  DATE 2010»
14 years 1 months ago
Efficient High-Level modeling in the networking domain
-- Starting Electronic System Level (ESL) design flows with executable High-Level Models (HLMs) has the potential to sustainably improve productivity. However, writing good HLMs fo...
Christian Zebelein, Joachim Falk, Christian Haubel...
MICRO
1999
IEEE
71views Hardware» more  MICRO 1999»
14 years 1 months ago
Selective Cache Ways: On-Demand Cache Resource Allocation
Increasing levels of microprocessor power dissipation call for new approaches at the architectural level that save energy by better matching of on-chip resources to application re...
David H. Albonesi
RSP
1999
IEEE
128views Control Systems» more  RSP 1999»
14 years 1 months ago
3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems
The advances in the programmable hardware has lead to new architectures where the hardware can be dynamically adapted to the application to gain better performance. There are stil...
Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh
ITC
1997
IEEE
121views Hardware» more  ITC 1997»
14 years 1 months ago
BIST-Based Diagnostics of FPGA Logic Blocks
: Accurate diagnosis is an essential requirement in many testing environments, since it is the basis for any repair or replacement strategy used for chip or system fault-tolerance....
Charles E. Stroud, Eric Lee, Miron Abramovici
ISLPED
1996
ACM
83views Hardware» more  ISLPED 1996»
14 years 28 days ago
12-b 125 MSPS CMOS D/A designed for spectral performance
A 12-b 125 MSPS, digital to analog converter fabricated on a 0.6 micron single poly double metal CMOS process is presented. The design operates on supply voltages from 2.7 to 5.5 ...
Douglas Mercer, Larry Singer