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» Database Architectures for New Hardware
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SC
1995
ACM
14 years 8 days ago
A Performance Evaluation of the Convex SPP-1000 Scalable Shared Memory Parallel Computer
The Convex SPP-1000 is the first commercial implementation of a new generation of scalable shared memory parallel computers with full cache coherence. It employs a hierarchical s...
Thomas L. Sterling, Daniel Savarese, Peter MacNeic...
PDPTA
2004
13 years 10 months ago
Design of a Real-Time Scheduler for Kahn Process Networks on Multiprocessor Systems
High-throughput real-time systems require non-standard and costly hardware and software solutions. Modern workstation can represent a credible alternative to develop realtime inte...
Javed Dulloo, Philippe Marquet
CONIELECOMP
2011
IEEE
13 years 16 days ago
DSRP: Distributed SensorWeb Routing Protocol
—We propose a new multi-hop routing protocol for wireless sensor networks, suited for monitoring and control applications. The aim of this research is to adapt flat and hierarch...
Abhinav Valada, David Kohanbash, George Kantor
DAC
2003
ACM
14 years 9 months ago
Coverage directed test generation for functional verification using bayesian networks
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or...
Shai Fine, Avi Ziv
DAC
2006
ACM
14 years 9 months ago
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors i...
John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S....