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FPL
2009
Springer
79views Hardware» more  FPL 2009»
14 years 9 days ago
A reconfigurable architecture for the Phylogenetic Likelihood Function
As FPGA devices become larger, more coarse-grain modules coupled with large scale reconfigurable fabric become available, thus enabling new classes of applications to run effici...
Nikolaos Alachiotis, Alexandros Stamatakis, Euripi...
DATE
2008
IEEE
79views Hardware» more  DATE 2008»
14 years 2 months ago
System Performance Optimization Methodology for Infineon's 32-Bit Automotive Microcontroller Architecture
Microcontrollers are the core part of automotive Electronic Control Units (ECUs). A significant investment of the ECU manufacturers and even their customers is linked to the speci...
Albrecht Mayer, Frank Hellwig
ITCC
2005
IEEE
14 years 1 months ago
A Parallelized Design for an Elliptic Curve Cryptosystem Coprocessor
In many applications a software implementation of ECC (Elliptic Curve Cryptography) might be inappropriate due to performance requirements, therefore hardware implementations are ...
Fabio Sozzani, Guido Bertoni, Stefano Turcato, Luc...
DATE
1999
IEEE
85views Hardware» more  DATE 1999»
14 years 14 hour ago
At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks
As an at-speed solution to board-level interconnect testing, an enhanced boundary-scan architecture utilizing a combination of slightly modified boundary-scan cells and a user-def...
Jongchul Shin, Hyunjin Kim, Sungho Kang
TEC
2002
103views more  TEC 2002»
13 years 7 months ago
Immunotronics - novel finite-state-machine architectures with built-in self-test using self-nonself differentiation
A novel approach to hardware fault tolerance is demonstrated that takes inspiration from the human immune system as a method of fault detection. The human immune system is a remark...
D. W. Bradley, Andrew M. Tyrrell