Search Sciweavers | Sciweavers

165 search results - page 6 / 33

» Dataflow Architectures for GALS

click to vote

CODES
2005
IEEE

92views Software Engineering» more CODES 2005»

Designing real-time H.264 decoders with dataflow architectures

14 years 4 months ago

Download www.cecs.uci.edu

High performance microprocessors are designed with generalpurpose applications in mind. When it comes to embedded applications, these architectures typically perform controlintens...

Youngsoo Kim, Suleyman Sair

claim paper

Read More »

click to vote

JUCS
2000

120views more JUCS 2000»

Execution and Cache Performance of the Scheduled Dataflow Architecture

13 years 10 months ago

Download www.dii.unisi.it

: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...

Krishna M. Kavi, Joseph Arul, Roberto Giorgi

claim paper

Read More »

click to vote

ISCA
2006
IEEE

130views Hardware» more ISCA 2006»

Area-Performance Trade-offs in Tiled Dataflow Architectures

13 years 10 months ago

Download wavescalar.cs.washington.edu

: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...

Steven Swanson, Andrew Putnam, Martha Mercaldi, Ke...

claim paper

Read More »

click to vote

HIPEAC
2009
Springer

109views System Software» more HIPEAC 2009»

Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures

14 years 5 months ago