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108
Voted
DATE
2003
IEEE
15 years 9 months ago
2003
IEEE
Circuit marginality failures in high performance VLSI circuits are projected to increase due to shrinking process geometries and high frequency design techniques. Capacitive cross...
125
Voted
DATE
2002
IEEE
15 years 8 months ago
2002
IEEE
A gate level, automated fault diagnosis scheme is proposed for scan-based BIST designs. The proposed scheme utilizes both fault capturing scan chain information and failing test v...
114
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DATE
2002
IEEE
15 years 8 months ago
2002
IEEE
This paper explores the role of data analysis methods to support system-level designers in characterising the performance of embedded applications. In particular, we address the p...
134
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DATE
2002
IEEE
15 years 8 months ago
2002
IEEE
Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...
127
Voted
DATE
2002
IEEE
15 years 8 months ago
2002
IEEE
We advocate a network on silicon (NOS) as a hardware architecture to implement communication between IP cores in future technologies, and as a software model in the form of a prot...