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126
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DATE
2009
IEEE
122views Hardware» more  DATE 2009»
15 years 10 months ago
Analysis and optimization of NBTI induced clock skew in gated clock trees
NBTI (Negative Bias Temperature Instability) has emerged as the dominant PMOS device failure mechanism for sub100nm VLSI designs. There is little research to quantify its impact o...
Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram...
118
Voted
DATE
2009
IEEE
113views Hardware» more  DATE 2009»
15 years 10 months ago
MPSoCs run-time monitoring through Networks-on-Chip
—Networks-on-Chip (NoCs) have appeared as design strategy to overcome the limitations, in terms of scalability, efficiency, and power consumption of current buses. In this paper...
Leandro Fiorin, Gianluca Palermo, Cristina Silvano
111
Voted
DATE
2009
IEEE
127views Hardware» more  DATE 2009»
15 years 10 months ago
Sequential logic synthesis using symbolic bi-decomposition
This paper uses under-approximation of unreachable states of a design to derive incomplete specification of combinational logic. The resulting incompletely-specified functions are...
Victor N. Kravets, Alan Mishchenko
131
Voted
DATE
2009
IEEE
149views Hardware» more  DATE 2009»
15 years 10 months ago
An ILP formulation for task mapping and scheduling on multi-core architectures
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...
Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tugh...
DATE
2008
IEEE
124views Hardware» more  DATE 2008»
15 years 10 months ago
Logic Synthesis with Nanowire Crossbar: Reality Check and Standard Cell-based Integration
Nanowire crossbar is one of the most promising circuit solutions for nanoelectronics. We show nanowire crossbars do not scale well in terms of logic density and speed. We conseque...
Mian Dong, Lin Zhong