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128
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DATE
2005
IEEE
15 years 9 months ago
2005
IEEE
Recent work on Differential Power Analysis shows that even mathematically-secure cryptographic protocols may be vulnerable at the physical implementation level. By measuring energ...
133
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DATE
2005
IEEE
15 years 9 months ago
2005
IEEE
Accurate timing analysis is key to efficient embedded system synthesis and integration. While industrial control software systems are developed using graphical models, such as Ma...
103
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DATE
2005
IEEE
15 years 9 months ago
2005
IEEE
A method to generate test patterns referred to as defect aware test patterns is proposed. Defect aware test patterns have greater ability to detect un-modeled defects. The propose...
185
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DATE
2003
IEEE
15 years 9 months ago
2003
IEEE
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
91
Voted
DATE
2003
IEEE
15 years 9 months ago
2003
IEEE
A system-on-chip lock cache (SoCLC) is an intellectual property (IP) core that provides effective lock synchronization in a heterogeneous multiprocessor shared-memory system-on-ac...