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DATE
2000
IEEE
88views Hardware» more  DATE 2000»
15 years 8 months ago
Techniques for Reducing Read Latency of Core Bus Wrappers
Today’s system-on-a-chip designs consist of many cores. To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic sep...
Roman L. Lysecky, Frank Vahid, Tony Givargis
DATE
2004
IEEE
109views Hardware» more  DATE 2004»
15 years 7 months ago
RTL Processor Synthesis for Architecture Exploration and Implementation
Architecture description languages are widely used to perform architecture exploration for application-driven designs, whereas the RT-level is the commonly accepted level for hard...
Oliver Schliebusch, Anupam Chattopadhyay, Rainer L...
DATE
2004
IEEE
126views Hardware» more  DATE 2004»
15 years 7 months ago
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...
Montek Singh, Michael Theobald
CA
2003
IEEE
15 years 9 months ago
Agent Chameleons: Agent Minds and Bodies
Agent design has to date concerned itself with the issues pertaining to a single body embedded in a single environment, whether virtual or real. This paper discusses the notion of...
Brian R. Duffy, Gregory M. P. O'Hare, Alan N. Mart...
AGI
2008
15 years 5 months ago
VARIAC: an Autogenous Cognitive Architecture
Learning theory and programs to date are inductively bounded: they can be described as "wind-up toys" which can only learn the kinds of things that their designers envisi...
J. Storrs Hall