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DATE
2007
IEEE
95views Hardware» more  DATE 2007»
15 years 10 months ago
A multi-core debug platform for NoC-based systems
Network-on-Chip (NoC) is generally regarded as the most promising solution for the future on-chip communication scheme in gigascale integrated circuits. As traditional debug archi...
Shan Tang, Qiang Xu
DATE
2006
IEEE
100views Hardware» more  DATE 2006»
15 years 10 months ago
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
Luciano Bononi, Nicola Concer
DATE
2006
IEEE
157views Hardware» more  DATE 2006»
15 years 10 months ago
Modeling and simulation of mobile gateways interacting with wireless sensor networks
Sensor networks are emerging wireless technologies; their integration with the existing 2.5G, 3G mobile networks is a key issue to provide advanced services, e.g., health control....
Franco Fummi, Davide Quaglia, Fabio Ricciato, Maur...
DATE
2006
IEEE
110views Hardware» more  DATE 2006»
15 years 10 months ago
Multiprocessor synthesis for periodic hard real-time tasks under a given energy constraint
The energy-aware design for electronic systems has been an important issue in hardware and/or software implementations, especially for embedded systems. This paper targets a synth...
Heng-Ruey Hsu, Jian-Jia Chen, Tei-Wei Kuo
DATE
2006
IEEE
124views Hardware» more  DATE 2006»
15 years 10 months ago
Timing-driven cell layout de-compaction for yield optimization by critical area minimization
This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard ...
Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada