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130
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DATE
2005
IEEE
15 years 10 months ago
2005
IEEE
: - One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at...
124
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DATE
2005
IEEE
15 years 10 months ago
2005
IEEE
Overheating has been acknowledged as a major issue in testing complex SOCs. Several power constrained system-level DFT solutions (power constrained test scheduling) have recently ...
118
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DATE
2005
IEEE
15 years 10 months ago
2005
IEEE
— A formal methodology for the analysis of a closed loop clock distribution and active deskewing network is proposed. In this paper an active clock distribution and deskewing net...
112
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DATE
2005
IEEE
15 years 10 months ago
2005
IEEE
One of the greatest impediments to achieving high quality placements using force-directed methods lies in the large amount of overlap initially present in these techniques. This o...
120
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DATE
2005
IEEE
15 years 10 months ago
2005
IEEE
As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been ide...