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DATE
2009
IEEE
83views Hardware» more  DATE 2009»
14 years 3 months ago
Performance-driven dual-rail insertion for chip-level pre-fabricated design
In recent years, pre-fabricated design styles grow up rapidly to amortize the mask cost. However, the interconnection delay of the pre-fabricated design styles slows down the circ...
Fu-Wei Chen, Yi-Yu Liu
DATE
2009
IEEE
109views Hardware» more  DATE 2009»
14 years 3 months ago
A design methodology for fully reconfigurable Delta-Sigma data converters
This paper presents a design methodology for fully reconfigurable low-voltage Delta-Sigma converters as for instance used in next-generation wireless applications. The design metho...
Yi Ke, Jan Craninckx, Georges G. E. Gielen
DATE
2009
IEEE
209views Hardware» more  DATE 2009»
14 years 3 months ago
A graph grammar based approach to automated multi-objective analog circuit design
— This paper introduces a graph grammar based approach to automated topology synthesis of analog circuits. A grammar is developed to generate circuits through production rules, t...
Angan Das, Ranga Vemuri
DATE
2008
IEEE
126views Hardware» more  DATE 2008»
14 years 3 months ago
Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits
Metallic Carbon Nanotubes (CNTs) create source-drain shorts in Carbon Nanotube Field Effect Transistors (CNFETs), causing excessive leakage, degraded noise margin and delay variat...
Jie Zhang, Nishant Patil, Subhasish Mitra
DATE
2006
IEEE
151views Hardware» more  DATE 2006»
14 years 2 months ago
An 830mW, 586kbps 1024-bit RSA chip design
This paper presents an RSA hardware design that simultaneously achieves high-performance and lowpower. A bit-oriented, split modular multiplication algorithm and architecture are ...
Chingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shy...