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126
Voted
DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
— Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way th...
116
Voted
DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
The automated design of SoCs from pre-selected IPs that may require different clocks is challenging because of the following issues. Firstly, protocol mismatches between IPs need ...
108
Voted
DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
Abstract—Building highly optimized embedded systems demands hardware/software (HW/SW) co-design. A key challenge in co-design is the design of HW/SW interfaces, which is often a ...
174
click to vote
DATE
2007
IEEE
15 years 9 months ago
2007
IEEE
Solid frameworks and toolkits for design and analysis of embedded systems are of high importance, since they enable early reasoning about critical properties of a system. This pap...
DATE
2007
IEEE
15 years 9 months ago
2007
IEEE
An important aspect of Design for Yield for embedded SRAM is identifying the expected worst case behavior in order to guarantee that sufficient design margin is present. Previousl...