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DATE
2007
IEEE
134views Hardware» more  DATE 2007»
14 years 2 months ago
Non-fractional parallelism in LDPC decoder implementations
Because of its excellent bit-error-rate performance, the Low-Density Parity-Check (LDPC) decoding algorithm is gaining increased attention in communication standards and literatur...
John Dielissen, Andries Hekstra
SIPS
2007
IEEE
14 years 1 months ago
Design and Analysis of LDPC Decoders for Software Defined Radio
Low Density Parity Check (LDPC) codes are one of the most promising error correction codes that are being adopted by many wireless standards. This paper presents a case study for ...
Sangwon Seo, Trevor N. Mudge, Yuming Zhu, Chaitali...
DATE
2009
IEEE
170views Hardware» more  DATE 2009»
14 years 2 months ago
A novel LDPC decoder for DVB-S2 IP
Abstract—In this paper a programmable Forward Error Correction (FEC) IP for a DVB-S2 receiver is presented. It is composed of a Low-Density Parity Check (LDPC), a Bose-ChaudhuriH...
Stefan Müller 0004, Manuel Schreger, Marten K...
ICASSP
2011
IEEE
12 years 11 months ago
A methodology based on Transportation problem modeling for designing parallel interleaver architectures
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...
Awais Sani, Philippe Coussy, Cyrille Chavet, Eric ...
DFT
2007
IEEE
135views VLSI» more  DFT 2007»
14 years 2 months ago
Fault Secure Encoder and Decoder for Memory Applications
We introduce a reliable memory system that can tolerate multiple transient errors in the memory words as well as transient errors in the encoder and decoder (corrector) circuitry....
Helia Naeimi, André DeHon