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ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
13 years 9 months ago
Reconfigurable Shuffle Network Design in LDPC Decoders
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
Jun Tang, Tejas Bhatt, Vishwas Sundaramurthy
ICC
2007
IEEE
192views Communications» more  ICC 2007»
14 years 2 months ago
Informed Dynamic Scheduling for Belief-Propagation Decoding of LDPC Codes
— Low-Density Parity-Check (LDPC) codes are usually decoded by running an iterative belief-propagation, or message-passing, algorithm over the factor graph of the code. The tradi...
Andres I. Vila Casado, Miguel Griot, Richard D. We...
VTC
2008
IEEE
14 years 2 months ago
Construction of Regular Quasi-Cyclic Protograph LDPC codes based on Vandermonde Matrices
Abstract— In this contribution, we investigate the attainable performance of quasi-cyclic (QC) protograph Low-Density Parity-Check (LDPC) codes for transmission over both Additiv...
Nicholas Bonello, Sheng Chen, Lajos Hanzo
ISCAS
2006
IEEE
100views Hardware» more  ISCAS 2006»
14 years 1 months ago
Decoders for low-density parity-check convolutional codes with large memory
— Low-density parity-check convolutional codes offer the same good error-correcting performance as low-density parity-check block codes while having the ability to encode and dec...
Stephen Bates, L. Gunthorpe, Ali Emre Pusane, Zhen...
ISCAS
2008
IEEE
111views Hardware» more  ISCAS 2008»
14 years 2 months ago
Low-power traceback MAP decoding for double-binary convolutional turbo decoder
—Convolutional turbo decoding requires large data access and consumes large memories. To reduce the size of the metrics memory, the traceback MAP decoding is introduced for doubl...
Cheng-Hung Lin, Chun-Yu Chen, An-Yeu Wu