67 search results - page 11 / 14 » Defect Aware Test Patterns |
ASPDAC
2009
ACM
14 years 1 months ago
2009
ACM
Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologie...
ITC
2003
IEEE
14 years 20 days ago
2003
IEEE
Very Deep Sub-Micron (VDSM) defects are resolved as Statistical Post-Processing™ (SPP) outliers of a new IDDQ screen. The screen applies an IDDQ pattern once to the Device Under...
ETS
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper summarizes advanced test patterns designed to target dynamic and time-related faults caused by new defect mechanisms in deep-submicron memory technologies. Such tests a...
PICS
2001
13 years 8 months ago
2001
Banding can be a major defect in inkjet printing. Knowing the visual sensitivity threshold of inkjet banding is therefore useful for understanding and pushing the technological li...
IOLTS
2000
IEEE
13 years 11 months ago
2000
IEEE
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...