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» Defect Aware Test Patterns
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DATE
2009
IEEE
106views Hardware» more  DATE 2009»
14 years 2 months ago
Generation of compact test sets with high defect coverage
Abstract-Multi-detect (N-detect) testing suffers from the drawback that its test length grows linearly with N. We present a new method to generate compact test sets that provide hi...
Xrysovalantis Kavousianos, Krishnendu Chakrabarty
PICS
2003
13 years 8 months ago
Prediction of Print Defect Perception
This study examines the prediction of print defect perception (banding) of the human visual system (HVS) by combining detection probabilities of contrast components from wavelet a...
Kevin D. Donohue, M. Vijay Venkatesh, Chengwu Cui
VTS
2008
IEEE
119views Hardware» more  VTS 2008»
14 years 1 months ago
Error Sequence Analysis
With increasing IC process variation and increased operating speed, it is more likely that even subtle defects will lead to the malfunctioning of a circuit. Various fault models, ...
Jaekwang Lee, Intaik Park, Edward J. McCluskey
DAC
2000
ACM
14 years 8 months ago
Self-test methodology for at-speed test of crosstalk in chip interconnects
The effect of crosstalk errors is most significant in highperformance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that...
Xiaoliang Bai, Sujit Dey, Janusz Rajski
IWANN
1995
Springer
13 years 11 months ago
Test Pattern Generation for Analog Circuits Using Neural Networks and Evolutive Algorithms
This paper presents a comparative analysis of neural networks, simulated annealing, and genetic algorithms in the determination of input patterns for testing analog circuits. The ...
José Luis Bernier, Juan J. Merelo Guerv&oac...