Error Sequence Analysis

With increasing IC process variation and increased operating speed, it is more likely that even subtle defects will lead to the malfunctioning of a circuit. Various fault models, such as the transition fault model and the path-delay model, have been used to aid delay defect detection. However, these models are not efficient for small-delay defect coverage or for test pattern generation time. Error sequence analysis utilizes the order in which the errors occur during a frequency sweep of a transition test to identify smalldelay defects that may escape the same test applied in the conventional way. Moreover, it can detect such defects even in the presence of inter-die process variations, such as lot-to-lot and wafer-to-wafer process variation. In addition, error sequence analysis is very effective in separating devices with delay defects from devices that have failed due to process variation.

• Type: Conference
• Year: 2008
• Where: VTS
• Authors: Jaekwang Lee, Intaik Park, Edward J. McCluskey
• Keywords: Delay Defects, Error Sequence Analysis, Process Variation, VLSI, VTS 2008