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» Defect Tolerance in Multiple-FPGA Systems
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FCCM
2006
IEEE
106views VLSI» more  FCCM 2006»
14 years 2 months ago
Defect-Tolerant Nanocomputing Using Bloom Filters
We propose a novel defect-tolerant design methodology using Bloom filters for defect mapping for nanoscale computing devices. It is a general approach that can be used for any pe...
Gang Wang, Wenrui Gong, Ryan Kastner
DFT
2008
IEEE
89views VLSI» more  DFT 2008»
14 years 3 months ago
Fabrication Variations and Defect Tolerance for Nanomagnet-Based QCA
Tolerating defects and fabrication variations will be critical in any system made with devices that have nanometer feature sizes. This paper considers how fabrication variations a...
Michael T. Niemier, Michael Crocker, Xiaobo Sharon...
CODES
2008
IEEE
13 years 10 months ago
Design and defect tolerance beyond CMOS
It is well recognized that novel computational models, devices and technologies are needed in order to sustain the remarkable advancement of CMOS-based VLSI circuits and systems. ...
Xiaobo Sharon Hu, Alexander Khitun, Konstantin K. ...
ICCD
2003
IEEE
113views Hardware» more  ICCD 2003»
14 years 5 months ago
Exploiting Microarchitectural Redundancy For Defect Tolerance
Continued advancements in fabrication technology and reductions in feature size create challenges in maintaining both manufacturing yield rates and long-term reliability of device...
Premkishore Shivakumar, Stephen W. Keckler, Charle...
TC
1998
13 years 8 months ago
Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
—The very high levels of integration and submicron device sizes used in current and emerging VLSI technologies for FPGAs lead to higher occurrences of defects and operational fau...
Fran Hanchek, Shantanu Dutt