424 search results - page 34 / 85 » Delay modelling improvement for low voltage applications |
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
Interconnection networks in Systems-On-Chip begin to have a non-negligible impact on the power consumption of a whole system. This is because of increasing inter-wire capacitances...
ICC
2007
IEEE
14 years 2 months ago
2007
IEEE
— We target M-ary data sequence estimation over time-variant frequency selective fading channels subject to cochannel interference (CCI). A novel joint reduced state sequence est...
DSD
2007
IEEE
14 years 2 months ago
2007
IEEE
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
ECCTD
2011
12 years 7 months ago
2011
⎯ Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate th...
CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
Future embedded and wireless devices will be increasingly powerful supporting many applications including one of the most crucial, security. Although many wireless and embedded de...