38 search results - page 4 / 8 » Delay-Insensitive Ternary Logic |
DDECS
2009
IEEE
14 years 1 months ago
2009
IEEE
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...
JOLLI
2008
13 years 6 months ago
2008
In this paper, consistency is understood as the absence of the negation of a theorem, and not, in general, as the absence of any contradiction. We define the basic constructive log...
ISMVL
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper we present fault tolerant CMOS logic using redundancy and ternary signals. The ternary gates are implemented using recharge logic which can be exploited in binary an...
BIRTHDAY
2004
Springer
14 years 3 days ago
2004
Springer
Ternary algebra has been used for detection of hazards in logic circuits since 1948. Process spaces have been introduced in 1995 act models of concurrent processes. Surprisingly, p...
APAL
2004
13 years 6 months ago
2004
Modus ponens provides the central theme. There are laws, of the form A C. A logic (or other theory) L collects such laws. Any datum A (or theory T incorporating such data) provid...