86 search results - page 12 / 18 » Delay-Reduced Combinational Logic Synthesis using Multiplexe... |
CCE
2008
13 years 9 months ago
2008
This paper proposes a new MINLP model for heat exchanger network synthesis that includes streams with phase change. The model considers every possible combination of process strea...
ICCAD
2002
IEEE
14 years 6 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
JNSM
2008
13 years 9 months ago
2008
There is a large conceptual gap between end-to-end infrastructure requirements and detailed component configuration implementing those requirements. Today, this gap is manually br...
VTS
2007
IEEE
14 years 3 months ago
2007
IEEE
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. Test points are iden...
DATE
2008
IEEE
14 years 4 months ago
2008
IEEE
Multi-input addition is an important operation for many DSP and video processing applications. On FPGAs, multi-input addition has traditionally been implemented using trees of car...