86 search results - page 16 / 18 » Delay-Reduced Combinational Logic Synthesis using Multiplexe... |
DAC
2001
ACM
14 years 9 months ago
2001
ACM
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuit...
ICCAD
1995
IEEE
14 years 3 days ago
1995
IEEE
This paper describes two techniques to quantify energy consumption of burst-modeasynchronous(clock-less)controlcircuits. The circuit specifications consideredare extended burst-m...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
SAT sweeping is a method for simplifying an AND/INVERTER graph (AIG) by systematically merging graph vertices from the inputs towards the outputs using a combination of structural...
DAC
2000
ACM
14 years 9 months ago
2000
ACM
In this paper, we propose a technique to implement communication protocols as hardware circuits using a model of concurrent EFSMs with multi-way synchronization. Since use of mult...
DAC
2007
ACM
14 years 9 months ago
2007
ACM
An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is...