86 search results - page 8 / 18 » Delay-Reduced Combinational Logic Synthesis using Multiplexe... |
DAC
2006
ACM
14 years 10 months ago
2006
ACM
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
ACSD
2010
IEEE
13 years 7 months ago
2010
IEEE
Self-timed circuits present an attractive solution to the problem of process variation. However, implementing selftimed combinational logic can be complex and expensive. This pape...
WCE
2007
13 years 10 months ago
2007
- In the speed-independent logic, the hazards caused by input inverters are identified. The known methods of the elimination of such hazards are based on avoiding input inverters. ...
ICCD
1992
IEEE
14 years 1 months ago
1992
IEEE
We describe a new synthesis procedure for designing asynchronous controllers from burst-mode specifications, a class of specifications allowing multiple input change fundamental m...
FPL
2006
Springer
14 years 1 months ago
2006
Springer
This paper presents a novel tool flow combining rewriting logic with hardware synthesis. It enables the automated generation of synthesizable VHDL code from mathematical equations...