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ARITH
2009
IEEE
15 years 10 months ago
Challenges in Automatic Optimization of Arithmetic Circuits
Despite the impressive progress of logic synthesis in the past decade, finding the best architecture for a given circuit still remains an open and largely unsolved problem, espec...
Ajay K. Verma, Philip Brisk, Paolo Ienne
ATAL
2006
Springer
15 years 7 months ago
Designing agent chips
We outline meta-encoding schemas for compiling nonmonotonic logic theories into Verilog HDL (Hardware Description Language) descriptions. These descriptions can be synthesized int...
Insu Song, Guido Governatori
CADE
2006
Springer
16 years 4 months ago
A Resolution-Based Decision Procedure for SHOIQ
We present a resolution-based decision procedure for the description logic SHOIQ--the logic underlying the Semantic Web ontology language OWL-DL. Our procedure is goal-oriented, an...
Yevgeny Kazakov, Boris Motik
BIRTHDAY
2009
Springer
15 years 10 months ago
Foundations of Temporal Conceptual Data Models
Abstract. This chapter considers the different temporal constructs appeared in the literature of temporal conceptual models (timestamping and evolution constraints), and it provid...
Alessandro Artale, Enrico Franconi
CADE
2005
Springer
15 years 9 months ago
KRHyper - In Your Pocket
Abstract. Pocket KRHyper is a reasoning system for Java-enabled mobile devices. The core of the system is a first order theorem prover and model generator based on the hyper table...
Alex Sinner, Thomas Kleemann