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SASP
2008
IEEE
183views Hardware» more  SASP 2008»
14 years 2 months ago
Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor
Different approaches have been proposed over the years for automatically transforming High-Level-Languages (HLL) descriptions of applications into custom hardware implementations. ...
Alexandros Papakonstantinou, Deming Chen, Wen-mei ...
ENTCS
2007
122views more  ENTCS 2007»
13 years 7 months ago
Plugging a Space Leak with an Arrow
The implementation of conceptually continuous signals in functional reactive programming (FRP) is studied in detail. We show that recursive signals in standard implementations usi...
Hai Liu, Paul Hudak
PLDI
2010
ACM
14 years 28 days ago
Decoupled lifeguards: enabling path optimizations for dynamic correctness checking tools
Dynamic correctness checking tools (a.k.a. lifeguards) can detect a wide array of correctness issues, such as memory, security, and concurrency misbehavior, in unmodified executa...
Olatunji Ruwase, Shimin Chen, Phillip B. Gibbons, ...
CASES
2007
ACM
13 years 12 months ago
Fragment cache management for dynamic binary translators in embedded systems with scratchpad
Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for e...
José Baiocchi, Bruce R. Childers, Jack W. D...
ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
14 years 1 months ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan