135 search results - page 5 / 27 » Design, layout and verification of an FPGA using automated t... |
ICCAD
1997
IEEE
13 years 12 months ago
1997
IEEE
This paper presents a unique approach to improve yield given a routed layout. Currently after routing has been completed and compacted, it generally proceeds to verification witho...
FPL
2000
Springer
13 years 11 months ago
2000
Springer
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
A tool that automates the floating-point to fixed-point conversion (FFC) process for digital signal processing systems is described. The tool automatically optimizes fixed-point d...
DAC
1991
ACM
13 years 11 months ago
1991
ACM
REX is a program that extracts parasitic resistance and capacitance values for nodes in VLSI layouts. REX also performs network serial and parallel simplifications. Two types of n...