135 search results - page 9 / 27 » Design, layout and verification of an FPGA using automated t... |
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
LCTRTS
1999
Springer
13 years 12 months ago
1999
Springer
We present a design tool for automated synthesis of embedded systems on distributed COTS-based platforms. Our synthesis tool consists of (1) a graphical user interface for input o...
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
Emerging heterogeneous multiprocessors will have custom memory and bus architectures that must balance resource sharing and system partitioning to meet cost constraints. We propos...
FPGA
2006
ACM
13 years 11 months ago
2006
ACM
In this paper, we propose a technique to flexibly implement genetic algorithms for various problems on FPGAs. For the purpose, we propose a basic architecture for GA which consist...
FPL
2004
Springer
14 years 1 months ago
2004
Springer
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...