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ISLPED
2010
ACM
128views Hardware» more  ISLPED 2010»
13 years 5 months ago
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
DRAM power and energy efficiency considerations are becoming increasingly important for low-power and mobile systems. Using lower power modes provided by commodity DRAM chips redu...
Ahmed M. Amin, Zeshan Chishti
TVLSI
2010
13 years 2 months ago
A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors
A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost, flexible routing capability, and supports globally asynchronous loc...
Zhiyi Yu, Bevan M. Baas
TVLSI
2008
207views more  TVLSI 2008»
13 years 7 months ago
Effective Radii of On-Chip Decoupling Capacitors
Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the white space available on a die or place...
Mikhail Popovich, Michael Sotman, Avinoam Kolodny,...
DAC
2011
ACM
12 years 7 months ago
DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips
As transistor dimensions continue to scale deep into the nanometer regime, silicon reliability is becoming a chief concern. At the same time, transistor counts are scaling up, ena...
Andrew DeOrio, Konstantinos Aisopos, Valeria Berta...
HICSS
2006
IEEE
164views Biometrics» more  HICSS 2006»
14 years 1 months ago
A Methodology for Generating Application-Specific Heterogeneous Processor Arrays
Hardware designers are increasingly turning to Single Chip Multi-Processors to achieve power and throughput goals. To further increase performance for a specific application the c...
Stephen D. Craven, Cameron Patterson, Peter M. Ath...