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HPCA
2003
IEEE
14 years 8 months ago
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
Wai Hong Ho, Timothy Mark Pinkston
ISVLSI
2002
IEEE
109views VLSI» more  ISVLSI 2002»
14 years 24 days ago
A Network on Chip Architecture and Design Methodology
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnn...
ACSD
2005
IEEE
121views Hardware» more  ACSD 2005»
14 years 1 months ago
LusSy: A Toolbox for the Analysis of Systems-on-a-Chip at the Transactional Level
We describe a toolbox for the analysis of Systems-on-achip described in SystemC at the transactional level. The tools are able to extract information from SystemC code, and to bui...
Matthieu Moy, Florence Maraninchi, Laurent Maillet...
CSREAESA
2006
13 years 9 months ago
Design and Implementation of SoPC with Multi-Bus on a Chip
SoPC (System on a Programmable Chip) is one important kind of SoC solution based on PLD (Programmable Logic Device). At the same time, PBD (Platform-based Design) has become popul...
Fangjun Jian, Jizhong Han, Chengde Han, Qin Zhang,...
NOMS
2002
IEEE
130views Communications» more  NOMS 2002»
14 years 24 days ago
Design of a network level management information model for automatically switched transport networks
The concept of Automatically Switched Transport Networks (ASTN) combines elements of distributed connection management from the IP world with classical transport network functiona...
Georg Lehr, Ulrike Hartmer, Ralf Geerdsen