123 search results - page 11 / 25 » Design For Testability Method for CML Digital Circuits |
PATMOS
2005
Springer
14 years 1 months ago
2005
Springer
This paper presents a modular optimization framework for custom digital circuits in the power – performance space. The method uses a static timer and a nonlinear optimizer to max...
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
Formal methods have been advocated for the verification of digital design where correctness is proved mathematically. In contrast to digital designs, the verification of analog ...
ASAP
1997
IEEE
13 years 12 months ago
1997
IEEE
Improvements in semiconductor integration density and the resulting problem of having to manage designs of increasing complexity is an old one, but still current. The new challeng...
ICCAD
1996
IEEE
13 years 12 months ago
1996
IEEE
The functional validation of a state-of-the-art digital design is usually performed by simulation of a register-transfer-level model. The degree to which the testvector suite cove...
DAC
2009
ACM
14 years 2 months ago
2009
ACM
For a computing system to be trusted, it is equally important to verify that the system performs no more and no less functionalities than desired. Traditional testing and verifica...