123 search results - page 16 / 25 » Design For Testability Method for CML Digital Circuits |
DAC
2002
ACM
14 years 8 months ago
2002
ACM
The ForSyDe methodology has been developed for system level design. In this paper we present formal transformation methods for the refinement of an abstract and formal system mode...
ISLPED
1997
ACM
13 years 12 months ago
1997
ACM
With the increasing performance and density of VLSI circuits as well as the popularity of portable devices such as personal digital assistance, power consumption has emerged as an...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g. due to environmental radiation. Approaches to implement fault tol...
DAC
2010
ACM
13 years 11 months ago
2010
ACM
—Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NP-hard ...
FPL
2004
Springer
14 years 1 months ago
2004
Springer
Abstract. Evolvable Hardware (EHW) is a scheme - inspired by natural evolution, for automatic design of hardware systems. By exploring a large design search space, EHW may find so...