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» Design Framework for Partial Run-Time FPGA Reconfiguration
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DAC
2000
ACM
14 years 8 months ago
Hardware-software co-design of embedded reconfigurable architectures
In this paper we describe a new hardware/software partitioning approach for embedded reconfigurable architectures consisting of a general-purpose processor (CPU), a dynamically re...
Yanbing Li, Tim Callahan, Ervan Darnell, Randolph ...
WCE
2007
13 years 9 months ago
High-Performance Multigrid Solvers in Reconfigurable Hardware
—Partial Differential Equations (PDEs) play an essential role in modeling real world problems. The broad field of modeling such systems has drawn the researchers’ attention for...
Safaa J. Kasbah, Issam W. Damaj
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
14 years 1 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
TVLSI
2010
13 years 2 months ago
Exploration of Heterogeneous FPGAs for Mapping Linear Projection Designs
In many applications, a reduction of the amount of the original data or a representation of the original data by a small set of variables is often required. Among many techniques, ...
Christos-Savvas Bouganis, Iosifina Pournara, Peter...
CDES
2006
158views Hardware» more  CDES 2006»
13 years 9 months ago
A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia