434 search results - page 32 / 87 » Design Methodologies and Architecture Solutions for High-Per... |
GLVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
Regularly structured design techniques can combat complexity on a variety of fronts. We present the Structured and Tuned Array Generation (STAG) design methodology, which provides...
DT
2006
13 years 7 months ago
2006
process: Designers must define higher abstraction levels that allow system modeling. They must use description languages that handle both hardware and software components to descri...
TC
2008
13 years 7 months ago
2008
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an ...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract— Shared memory is a common inter-processor communication paradigm for on-chip multiprocessor SoC (MPSoC) platforms. The latency overhead of switch-based interconnection ...