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DAC
2009
ACM
14 years 8 months ago
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
Shiyan Hu, Zhuo Li, Charles J. Alpert
ISCOPE
1999
Springer
13 years 12 months ago
Using Object-Oriented Techniques for Realizing Parallel Architectural Skeletons
The concept of design patterns has recently emerged as a new paradigm in the context of object-oriented design methodology. Similar ideas are being explored in other areas of compu...
Dhrubajyoti Goswami, Ajit Singh, Bruno R. Preiss
ASAP
2011
IEEE
233views Hardware» more  ASAP 2011»
12 years 7 months ago
Accelerating vision and navigation applications on a customizable platform
—The domain of vision and navigation often includes applications for feature tracking as well as simultaneous localization and mapping (SLAM). As these problems require computati...
Jason Cong, Beayna Grigorian, Glenn Reinman, Marco...
DAC
1995
ACM
13 years 11 months ago
Hierarchical Optimization of Asynchronous Circuits
Abstract— Many asynchronous designs are naturally specified and implemented hierarchically as an interconnection of separate asynchronous modules that operate concurrently and c...
Bill Lin, Gjalt G. de Jong, Tilman Kolks
DAC
2002
ACM
14 years 8 months ago
ILP-based engineering change
We have developed a generic integer linear programming(ILP)based engineering change(EC) methodology. The EC methodology has three components: enabling, fast, and preserving. Enabl...
Farinaz Koushanfar, Jennifer L. Wong, Jessica Feng...