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FPGA
1999
ACM
174views FPGA» more  FPGA 1999»
14 years 5 hour ago
Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs
Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimized towards specific applications...
Peter Kollig, Bashir M. Al-Hashimi
ASAP
2007
IEEE
153views Hardware» more  ASAP 2007»
13 years 8 months ago
Performance Evaluation of Adaptive Routing Algorithms for achieving Fault Tolerance in NoC Fabrics
Commercial designs are integrating from 10 to 100 embedded functional and storage blocks in a single system on chip (SoC) currently, and the number is likely to increase significa...
Haibo Zhu, Partha Pratim Pande, Cristian Grecu
ISAS
2004
Springer
14 years 1 months ago
A Modular Approach for Model-Based Dependability Evaluation of a Class of Systems
Analytical and simulative modeling for dependability and performance evaluation has been proven to be a useful and versatile approach in all the phases of the system life cycle. I...
Stefano Porcarelli, Felicita Di Giandomenico, Paol...
SIMUTOOLS
2008
13 years 9 months ago
An 802.16 model for NS2 simulator with an integrated QoS architecture
The IEEE 802.16 technology is emerging as a promising solution for BWA due to its ability to support multimedia services and to operate in multiple physical environments. Also, wi...
Ikbal Chammakhi Msadaa, Fethi Filali, Farouk Kamou...
IJNSEC
2008
106views more  IJNSEC 2008»
13 years 7 months ago
Parallel Hardware Architectures for the Cryptographic Tate Pairing
Identity-based cryptography uses pairing functions,which are sophisticated bilinear maps defined on elliptic curves.Computing pairings efficiently in software is presently a relev...
Guido Marco Bertoni, Luca Breveglieri, Pasqualina ...