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» Design Methodology and Manufacture of a Microinductor
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VTS
2000
IEEE
167views Hardware» more  VTS 2000»
13 years 11 months ago
Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis
The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in natur...
Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukher...
ICCAD
2004
IEEE
88views Hardware» more  ICCAD 2004»
14 years 4 months ago
Diagnosis of small-signal parameters for broadband amplifiers through S-parameter measurements and sensitivity-guided evolutiona
Kth increasing uncertainties in the modeling and pmcessing of semiconductor devices, it is essential that the sources of failures be identified once the devices ure manufactured I...
Fang Liu, Sule Ozev, Martin A. Brooke
DAC
1994
ACM
13 years 11 months ago
The Design of High-Performance Microprocessors at Digital
Today's high-performance single-chip CMOS microprocessors are the most complex and challenging chip designs ever implemented. To stay on the leading edge, Digital's micro...
Thomas F. Fox
ICCD
2004
IEEE
107views Hardware» more  ICCD 2004»
14 years 4 months ago
Network-on-Chip: The Intelligence is in The Wire
In this paper we describe how Network-on-Chip (NoC) will be the next major challenge to implementing complex and function-rich applications in advanced manufacturing processes at ...
Gérard Mas, Philippe Martin
FPGA
2008
ACM
184views FPGA» more  FPGA 2008»
13 years 9 months ago
Mapping for better than worst-case delays in LUT-based FPGA designs
Current advances in chip design and manufacturing have allowed IC manufacturing to approach the nanometer range. As the feature size scales down, greater variability is experience...
Kirill Minkovich, Jason Cong