Sciweavers

1734 search results - page 12 / 347
» Design Patterns for Reconfigurable Computing
Sort
View
IJES
2006
99views more  IJES 2006»
13 years 7 months ago
Dynamic reconfiguration for management of radiation-induced faults in FPGAs
This paper describes novel methods of exploiting the partial, dynamic reconfiguration capabilities of Xilinx Virtex V1000 FPGAs to manage single-event upset (SEU) faults due to rad...
Maya Gokhale, Paul Graham, Michael J. Wirthlin, Da...
MAM
2006
101views more  MAM 2006»
13 years 7 months ago
EPICURE: A partitioning and co-design framework for reconfigurable computing
This paper presents a new design methodology able to bridge the gap between an abstract specification and a heterogeneous recone architecture. The EPICURE contribution is the resu...
Jean-Philippe Diguet, Guy Gogniat, Jean Luc Philip...
CF
2004
ACM
14 years 28 days ago
The digital divide of computing
This presentation urges for creating more awareness of the impact of configware engineering onto embedded system development and examines the requirements of overdue CSE curricula...
Reiner W. Hartenstein
TIM
2010
188views Education» more  TIM 2010»
13 years 2 months ago
An Effective Framework to Evaluate Dynamic Partial Reconfiguration in FPGA Systems
Abstract--The most popular representative devices of reconfigurable computing are the Field Programmable Gate Arrays (FPGAs). A promising feature of an FPGA is the ability to reuse...
Kyprianos Papadimitriou, Antonis Anyfantis, Aposto...
FDL
2003
IEEE
14 years 24 days ago
Using Rewriting-Logic Notation for Funcional Verification in Data-Stream Based Reconfigurable Computing
Reconfigurable Systolic Arrays are a generalization of Systolic Arrays where node operations and interconnections can be redefined even at run time. This flexibility increases the...
Mauricio Ayala-Rincón, Ricardo P. Jacobi, C...