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» Design Patterns for Reconfigurable Computing
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137
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ASAP
2009
IEEE
131views Hardware» more  ASAP 2009»
15 years 7 months ago
Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system
This paper presents a new constraint-driven method for computational pattern selection, mapping and application scheduling using reconfigurable processor extensions. The presente...
Kevin Martin, Christophe Wolinski, Krzysztof Kuchc...
TACO
2008
130views more  TACO 2008»
15 years 2 months ago
Efficient hardware code generation for FPGAs
r acceptance of FPGAs as a computing device requires a higher level of programming abstraction. ROCCC is an optimizing C to HDL compiler. We describe the code generation approach i...
Zhi Guo, Walid A. Najjar, Betul Buyukkurt
109
Voted
RECONFIG
2009
IEEE
182views VLSI» more  RECONFIG 2009»
15 years 9 months ago
Scalability Studies of the BLASTn Scan and Ungapped Extension Functions
BLASTn is a ubiquitous tool used for large scale DNA analysis. Detailed profiling tests reveal that the most computationally intensive sections of the BLASTn algorithm are the sc...
Siddhartha Datta, Ron Sass
129
Voted
FPGA
1997
ACM
149views FPGA» more  FPGA 1997»
15 years 6 months ago
Signal Processing at 250 MHz Using High-Performance FPGA's
This paper describes an application in high-performance signal processing using reconfigurable computing engines: a 250 MHz cross-correlator for radio astronomy. Experimental resu...
Brian Von Herzen
ALT
1997
Springer
15 years 6 months ago
Learning One-Variable Pattern Languages Very Efficiently on Average, in Parallel, and by Asking Queries
A pattern is a string of constant and variable symbols. The language generated by a pattern is the set of all strings of constant symbols which can be obtained from by substituti...
Thomas Erlebach, Peter Rossmanith, Hans Stadtherr,...