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» Design Principles for Combiners with Memory
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ISCA
1999
IEEE
110views Hardware» more  ISCA 1999»
14 years 1 months ago
Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor
Providing adequate data bandwidth is extremely important for a wide-issue superscalar processor to achieve its full performance potential. Adding a large number of ports to a data...
Sangyeun Cho, Pen-Chung Yew, Gyungho Lee
ISCA
2011
IEEE
522views Hardware» more  ISCA 2011»
13 years 13 days ago
CPPC: correctable parity protected cache
Due to shrinking feature sizes processors are becoming more vulnerable to soft errors. Write-back caches are particularly vulnerable since they hold dirty data that do not exist i...
Mehrtash Manoochehri, Murali Annavaram, Michel Dub...
IPPS
2010
IEEE
13 years 6 months ago
Structuring the execution of OpenMP applications for multicore architectures
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
François Broquedis, Olivier Aumage, Brice G...
VLSID
2009
IEEE
96views VLSI» more  VLSID 2009»
14 years 9 months ago
Efficient Placement of Compressed Code for Parallel Decompression
Code compression is important in embedded systems design since it reduces the code size (memory requirement) and thereby improves overall area, power and performance. Existing res...
Xiaoke Qin, Prabhat Mishra
ICASSP
2009
IEEE
14 years 3 months ago
The gigavision camera
We propose a new image device called gigavision camera. The main differences between a conventional and a gigavision camera are that the pixels of the gigavision camera are binary...
Luciano Sbaiz, Feng Yang, Edoardo Charbon, Sabine ...