Sciweavers

401 search results - page 9 / 81
» Design Technology for Networked Reconfigurable FPGA Platform...
Sort
View
DAC
1996
ACM
15 years 7 months ago
Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design
In this paper, we study the problem of decomposing gates in fanin-unbounded or K-bounded networks such that the K-input LUT mapping solutions computed by a depthoptimal mapper hav...
Jason Cong, Yean-Yow Hwang
147
Voted
DATE
2005
IEEE
115views Hardware» more  DATE 2005»
15 years 9 months ago
An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs
This paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware. It resu...
Rui Rodrigues, João M. P. Cardoso
CODES
2009
IEEE
15 years 7 months ago
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems
Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhance...
Vincenzo Rana, Srinivasan Murali, David Atienza, M...
EUC
2007
Springer
15 years 7 months ago
Parallel Network Intrusion Detection on Reconfigurable Platforms
With the wide adoption of internet into our everyday lives, internet security becomes an important issue. Intrusion detection at the network level is an effective way of stopping m...
Chun Xue, Zili Shao, Meilin Liu, Qingfeng Zhuge, E...
140
Voted
FPGA
2006
ACM
141views FPGA» more  FPGA 2006»
15 years 7 months ago
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
This report describes a preliminary evaluation of possible performance of an FPGA-like architecture for future hybrid "CMOL" circuits which combine a semiconductor-trans...
Dmitri B. Strukov, Konstantin Likharev