665 search results - page 23 / 133 » Design and Analysis of a Dynamically Reconfigurable Network ... |
IPPS
2005
IEEE
14 years 2 months ago
2005
IEEE
Parallel random access memory, or PRAM, is a now venerable model of parallel computation that that still retains its usefulness for the design and analysis of parallel algorithms....
IPPS
2007
IEEE
14 years 3 months ago
2007
IEEE
: In this paper, we have proposed a time efficient, energy saving and robust broadcast/multicast protocol for reconfigurable cluster-based sensor network. In our broadcast protocol...
FPL
2006
Springer
14 years 20 days ago
2006
Springer
A modern SoC design comprises dozens of dedicated IP cores for specialized tasks and processors for generalpurpose tasks. Flexibility is the key feature of processors, since it is...
ASPDAC
2001
ACM
14 years 20 days ago
2001
ACM
Abstract- Avirtual interfacebetweenJava andFPGA for networked reconfigurationis presented. ThroughtheJavaflFPGAinterface,Java applicationscan exploithardwareaccelerators with FPGAs...
FPL
2010
Springer
13 years 7 months ago
2010
Springer
When utilizing reconfigurable hardware there are many applications that will require more memory than is available in a single hardware block. While FPGAs have tools and mechanisms...