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» Design and Analysis of a Robust Pipelined Memory System
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ISLPED
2005
ACM
88views Hardware» more  ISLPED 2005»
14 years 1 months ago
PARE: a power-aware hardware data prefetching engine
Aggressive hardware prefetching often significantly increases energy consumption in the memory system. Experiments show that a major fraction of prefetching related energy degrad...
Yao Guo, Mahmoud Ben Naser, Csaba Andras Moritz
SPAA
2010
ACM
14 years 15 days ago
Towards optimizing energy costs of algorithms for shared memory architectures
Energy consumption by computer systems has emerged as an important concern. However, the energy consumed in executing an algorithm cannot be inferred from its performance alone: i...
Vijay Anand Korthikanti, Gul Agha
EDBT
2008
ACM
135views Database» more  EDBT 2008»
14 years 7 months ago
Minimizing latency and memory in DSMS: a unified approach to quasi-optimal scheduling
Data Stream Management Systems (DSMSs) must support optimized execution scheduling of multiple continuous queries on massive, and frequently bursty, data streams. Previous approac...
Yijian Bai, Carlo Zaniolo
ISQED
2010
IEEE
137views Hardware» more  ISQED 2010»
13 years 5 months ago
Analysis of power supply induced jitter in actively de-skewed multi-core systems
This paper studies multi-core clock distribution using active deskewing methods. We propose an efficient methodology that uses Verilog-A to model PLLs, clock trees and power suppl...
Derek Chan, Matthew R. Guthaus
ISCA
2010
IEEE
222views Hardware» more  ISCA 2010»
13 years 9 months ago
Cohesion: a hybrid memory model for accelerators
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
John H. Kelm, Daniel R. Johnson, William Tuohy, St...