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TC
2010
13 years 6 months ago
Network-on-Chip Hardware Accelerators for Biological Sequence Alignment
—The most pervasive compute operation carried out in almost all bioinformatics applications is pairwise sequence homology detection (or sequence alignment). Due to exponentially ...
Souradip Sarkar, Gaurav Ramesh Kulkarni, Partha Pr...
ASAP
2009
IEEE
119views Hardware» more  ASAP 2009»
13 years 11 months ago
A Low Power High Performance Radix-4 Approximate Squaring Circuit
An implementation of a radix-4 approximate squaring circuit is described employing a new operand dual recoding technique. Approximate squaring circuits have numerous applications ...
Satyendra R. Datla, Mitchell A. Thornton, David W....
DAC
2010
ACM
13 years 11 months ago
Efficient fault simulation on many-core processors
Fault simulation is essential in test generation, design for test and reliability assessment of integrated circuits. Reliability analysis and the simulation of self-test structure...
Michael A. Kochte, Marcel Schaal, Hans-Joachim Wun...
ANCS
2008
ACM
13 years 9 months ago
A remotely accessible network processor-based router for network experimentation
Over the last decade, programmable Network Processors (NPs) have become widely used in Internet routers and other network components. NPs enable rapid development of complex packe...
Charlie Wiseman, Jonathan S. Turner, Michela Becch...
ASPLOS
2010
ACM
14 years 2 months ago
Accelerating the local outlier factor algorithm on a GPU for intrusion detection systems
The Local Outlier Factor (LOF) is a very powerful anomaly detection method available in machine learning and classification. The algorithm defines the notion of local outlier in...
Malak Alshawabkeh, Byunghyun Jang, David R. Kaeli