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DAC
2005
ACM
15 years 7 months ago
TCAM enabled on-chip logic minimization
This paper presents an efficient hardware architecture of an on-chip logic minimization coprocessor. The proposed architecture employs TCAM cells to provide fastest and memory e...
Seraj Ahmad, Rabi N. Mahapatra
ISCAS
2005
IEEE
121views Hardware» more  ISCAS 2005»
15 years 11 months ago
On-board fault-tolerant SAR processor for spaceborne imaging radar systems
A real-timehigh-performanceand fault-tolerantFPGA-based hardware architecture for the processing of synthetic apertureradar (SAR) images has been developed for advanced spaceborner...
Wai-Chi Fang, C. Le, S. Taft
ECBS
2003
IEEE
84views Hardware» more  ECBS 2003»
15 years 11 months ago
Model-Integrated Design Toolset for Polymorphous Computer-Based Systems
Polymorphous computer-based systems are systems in which the CPU architecture “morphs” or changes shape to meet the requirements of the application. Optimized and efficient de...
Brandon Eames, Ted Bapty, Ben Abbott, Sandeep Neem...
ICCBSS
2005
Springer
15 years 11 months ago
Resolving Architectural Mismatches of COTS Through Architectural Reconciliation
Abstract. The integration of COTS components into a system under development entails architectural mismatches. These have been tackled, so far, at the component level, through comp...
Paris Avgeriou, Nicolas Guelfi
ISCAS
2006
IEEE
122views Hardware» more  ISCAS 2006»
15 years 12 months ago
256-channel integrated neural interface and spatio-temporal signal processor
Abstract- We present an architecture and VLSI implemen- Various strategies in the analysis of spatio-temporal dynamtation of a distributed neural interface and spatio-temporal ics ...
J. N. Y. Aziz, Roman Genov, B. R. Bardakjian, M. D...