249 search results - page 28 / 50 » Design and Implementation of the NUMAchine Multiprocessor |
SIGMETRICS
2010
ACM
14 years 1 months ago
2010
ACM
We present S, the first system to provide transparent, lowoverhead application record-replay and the ability to go live from replayed execution. S i...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
This paper proposes a dynamic cache repartitioning technique that enhances compositionality on platforms executing media applications with multiple utilization scenarios. The repa...
CODES
2007
IEEE
14 years 2 months ago
2007
IEEE
This article presents a multiprocessor system-on-chip synthesis (MPSoC) algorithm that optimizes system mean time to failure. Given a set of directed acyclic periodic graphs of co...
DSN
2007
IEEE
14 years 2 months ago
2007
IEEE
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
ISCA
1998
IEEE
14 years 22 days ago
1998
IEEE
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a scalable and cost-effective mesh network at a constant cost per node. The MIT Al...