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» Design and Implementation of the TRIPS Primary Memory System
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TACAS
2007
Springer
105views Algorithms» more  TACAS 2007»
14 years 5 months ago
Hoare Logic for Realistically Modelled Machine Code
This paper presents a mechanised Hoare-style programming logic framework for assembly level programs. The framework has been designed to fit on top of operational semantics of rea...
Magnus O. Myreen, Michael J. C. Gordon
DATE
2010
IEEE
156views Hardware» more  DATE 2010»
14 years 4 months ago
Domain specific architecture for next generation wireless communication
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...
Botao Zhang, Hengzhu Liu, Heng Zhao, Fangzheng Mo,...
HPCA
2001
IEEE
14 years 11 months ago
An Architectural Evaluation of Java TPC-W
The use of the Java programming language for implementing server-side application logic is increasing in popularity, yet there is very little known about the architectural require...
Harold W. Cain, Ravi Rajwar, Morris Marden, Mikko ...
RAID
2009
Springer
14 years 5 months ago
Regular Expression Matching on Graphics Hardware for Intrusion Detection
The expressive power of regular expressions has been often exploited in network intrusion detection systems, virus scanners, and spam filtering applications. However, the flexibl...
Giorgos Vasiliadis, Michalis Polychronakis, Spyros...
ISCA
1994
IEEE
93views Hardware» more  ISCA 1994»
14 years 3 months ago
RAID-II: A High-Bandwidth Network File Server
In 1989, the RAID (Redundant Arrays of Inexpensive Disks) group at U. C. Berkeley built a prototype disk array called RAID-I. The bandwidth delivered to clients by RAID-I was seve...
Ann L. Drapeau, Ken Shirriff, John H. Hartman, Eth...