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CODES
2003
IEEE
14 years 2 months ago
Schedule-aware performance estimation of communication architecture for efficient design space exploration
In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined....
Sungchan Kim, Chaeseok Im, Soonhoi Ha
SASP
2008
IEEE
140views Hardware» more  SASP 2008»
14 years 3 months ago
An FPGA Design Space Exploration Tool for Matrix Inversion Architectures
— Matrix inversion is a common function found in many algorithms used in wireless communication systems. As FPGAs become an increasingly attractive platform for wireless communic...
Ali Irturk, Bridget Benson, Shahnam Mirzaei, Ryan ...
TPDS
2008
89views more  TPDS 2008»
13 years 8 months ago
Power/Performance/Thermal Design-Space Exploration for Multicore Architectures
Multicore architectures have been ruling the recent microprocessor design trend. This is due to different reasons: better performance, thread-level parallelism bounds in modern app...
Matteo Monchiero, Ramon Canal, Antonio Gonzá...
AAAI
1998
13 years 10 months ago
An Architecture for Exploring Large Design Spaces
We describe an architecture for exploring very large design spaces, for example, spaces that arise when design candidates are generated by combining components systematically from...
John R. Josephson, B. Chandrasekaran, Mark Carroll...
ASPLOS
2006
ACM
14 years 14 days ago
Efficiently exploring architectural design spaces via predictive modeling
Architects use cycle-by-cycle simulation to evaluate design choices and understand tradeoffs and interactions among design parameters. Efficiently exploring exponential-size desig...
Engin Ipek, Sally A. McKee, Rich Caruana, Bronis R...